1. Field of the Invention
The present invention relates to power management in integrated circuits, and more particularly to a method and apparatus for reducing power consumption in integrated circuits which are manufactured using technologies such as gallium arsenide (GaAs), which manages power consumed by sections of the circuit which operate at frequencies considerably lower than the system clock frequency.
2. Background of the Related Art
In the design of computers and other digital systems, engineers must often sacrifice power consumption to maximize speed of operation or vice versa. This is because these two parameters are nearly always inversely related. Other parameters such as noise margin can be sacrificed to limit power consumption but with adverse affects. Circuits manufactured using CMOS device technology tend to consume less power but typically achieve lower maximum frequencies of operation compared to circuits fabricated using other available technologies, such as bipolar silicon and gallium arsenide. The latter technologies, however, exhibit higher power consumption relative to CMOS circuits.
CMOS digital circuits consume less power because they employ a device structure which conducts current only during the time that the device is switching between a high and low binary output state. Once in either state, the device is virtually nonconductive. CMOS technology achieves this desirable characteristic by stacking two or more complimentary devices to produce a logic gate such that a p-channel device has its source coupled to the positive supply terminal of the circuit, has its gate and drain terminals coupled to the gate and drain terminals of an n-channel device respectively, and the source of the n-channel is coupled to the ground terminal of the circuit supply. It is significant that CMOS technology lends itself easily to producing p-channel and n-channel devices together in the same substrate because they are easily isolated by silicon oxide layers.
The above-described CMOS structure forms an inverter such that when the input of the inverter (i.e. the common gate terminals) is at or near 0 volts, the p-channel device turns on long enough to charge a capacitive load on the output of the inverter formed by the common drain terminals). Once the capacitance has been charged, there is no other path through which current can flow because the n-channel device is cut off and the input to the next logic device is one or more capacitive gates. Thus, once this state is reached no substantial current is flowing. When the input becomes equal to about the supply voltage, the p-channel cuts off, the n-channel device discharges the output capacitance to ground and again substantial current ceases to flow.
Continued advances in photolithography have provided steady reductions in circuit feature sizes, reducing bad capacitance and thus increasing the maximum frequency of operation of CMOS circuits. Of course, as CMOS circuits are driven at higher speeds, power dissipation goes up because the gates spend more time switching than in their nonconductive static states. Thus, while CMOS technology has begun challenging gallium arsenide technology for higher frequency applications, it has done so at the expense of power dissipation.
Prior art gallium arsenide (GaAs) circuits are still significantly faster than CMOS circuits but GaAs technology does not lend itself well to device implementations which can exploit the complimentary structure of CMOS devices. Further, transistor devices implemented in gallium arsenide, known as metal semiconductor field effect transistors (MESFETS), have parasitic Schottky diode structures coupled between their gate and source terminals as well as between their gate and drain terminals, which conduct current when properly biased. These parasitic Schottky diodes are inherent to the gallium arsenide manufacturing process. FIG. 1 illustrates a typical prior art GaAs Direct Coupled FET Logic (DCFL) inverter, comprising typical MESFETS 10 and 12, which drives another logic circuit the input of which is represented by MESFET 14. MESFET 10 is an n-channel device operated in the depletion mode so that a negative gate-to-source voltage is required for it to be cut off.
Because the gate and source of MESFET 10 are shorted, the depletion mode device conducts regardless of the voltage on output 20. Thus, when the input voltage of the inverter (as applied to the gate of MESFET 12) is a logic high, the input voltage is clamped at about 0.7 volts by the parasitic gate-to-source Schottky diode of load MESFET 12 (represented by diode 13). The output voltage on line 20 is then pulled low by MESFET 12 and the current supplied by MESFET 10 is conducted by MESFET 12 in the process. Because the gate-to-source voltage is close to zero for MESFET 14, it is cut off. Thus power is consumed the entire time that the inverter of FIG. 1 remains in this static state.
When the voltage applied to the gate of the transistor 12 is low (typically about 0.1 volts), MESFET 12 is cut off and output line 20 is pulled towards V.sub.cc and is clamped at about 0.7 volts by the parasitic gate-to-source Schottky diode 18 of load MESFET 14. Parasitic diode 18 now conducts the current sources by depletion mode MESFET 10. Thus, the typical GaAs logic gate consumes power both while switching and while in either static binary state.
A typical implementation of a very high-performance digital system uses a gallium arsenide circuit for those portions of the system requiring the highest speed of operation, while those portions of the system which do not have to operate at the highest frequencies are implemented on a CMOS chip, thereby reducing overall system power dissipation. This solution is not all that desirable because manufacturing two chips in two different technologies is inconvenient and more expensive, especially when both the high-speed and low-speed circuitry could otherwise be integrated onto the same chip.
Thus, attempts have been made in the past to minimize the power consumed by GaAs logic circuits and in particular, the GaAs circuitry which operates at lower maximum frequencies (i.e. typically &lt;10 MHz). One approach attempts to minimize the amount of current supplied by the depletion mode device (i.e. MESFET 10, FIG. 1). This has been accomplished with only marginal success by increasing its gate length and minimizing its gate width. The problem with this approach is that it increases the logic cell area as a result of the unusual device geometry that such an adjustment of the depletion mode device produces. Further, in gate arrays, device sizes are fixed and there are very few device geometrics to choose from.
Another known approach is to modify the process of manufacturing GaAs logic circuits to permit implementation of a complimentary design analogous to that of CMOS circuits. A type of p-channel MESFET device has been manufactured and implemented in complimentary fashion with an n-channel device to form inverter 21 as illustrated in FIG. 2. The p-channel device is a modulation doped heterostructure field effect transistor (pHFET) 22 and the n-channel is an all-implanted n-channel JFET 24. The output of the inverter 21 is coupled to the input of another logic gate (i.e inverter 23). FETS 24 and 26 still have the parasitic Schottky-type diodes as represented by diodes 28 and 30. Thus, when the input to inverter 21 is at a logic low, pHFET 22 supplies current through diode 30 of inverter 23.
To make this logic act more like CMOS, the supply voltage must be reduced towards the diode turn-on voltage of the n-channel JFET to reduce the current sourced by pHFET 22 while in the logic high state. This approach creates large variations in pull-up drive and power supply current due to the small voltage drop across the pHFET. Power dissipation increases substantially as the supply voltage is increased even a few tenths of a volt to increase noise margin (e.g. power dissipation has been shown to increase as much as twenty times when the voltage is increased from 0.8 volts to 1.2 volts). Additionally, processing is more difficult and costly because of the added complexity of manufacturing the pHFET device.
Another known approach to reducing power dissipation is to use a logic signal as the source of power for the depletion mode device of a logic gate, thus only dissipating significant power through the logic gate when the gate is needed for evaluation of its other logic input signals. Examples of an inverter 31 and a NOR gate 33 implemented using such an approach are shown in FIG. 3. When the A input is a logic high, the inverter 31 and the NOR gate 33 behave like conventional gates, with the depletion mode device 35 sourcing current to FETS 37 and 39 when the logic inputs are high, and sourcing current to the parasitic diode of the next gate when the logic input is a low. When the A input is a logic low, the output of the gate is maintained at a logic low with virtually no power dissipation, regardless of the value of the other logic inputs.
While this approach is good for combinational logic driven by enable signals, such as multiplexers, it is not that convenient for use with all of the combinational and sequential logic which might be employed in a gallium arsenide circuit. Moreover, this technique makes circuit design complex because a single depletion mode device might have to drive several "A" inputs which in turn may themselves drive several other "A" inputs and so on. Thus either special sizing of the depletion mode device is required, depending on the number of A inputs driven by a particular depletion mode device, or fan-out restrictions must be placed on the number of A inputs which can be driven by the outputs of such devices.
The prior art approaches for decreasing power consumption in GaAs circuits have considerable shortcomings and thus room exists in the art of GaAs circuit design to provide significant reductions in power dissipation without the above-described disadvantages. Because GaAs circuits are still faster than CMOS circuits, it is desirable to use GaAs devices in digital systems requiring very high speeds of operation. While CMOS technology has made big gains in speed of operation with commensurate increase in power dissipation, GaAs circuits still dissipate much more power than CMOS at frequencies below 50 MHz. Thus, it is highly desirable to reduce overall power consumption by GaAs circuits through management of power distributed to logic sections of GaAs circuits operating at lower maximum frequencies. This permits overall reductions in power consumption without compromising circuit speed, accuracy and cost of manufacture.